1. Field of the Invention
The present invention relates to a communication control device that may be applied to multiplex communication networks such as a Local Area Network (LAN) and the like and, more particularly, to a communication control device that may be widely, generally used for multiplex communication networks such as a LAN and the like.
2. Description of the Prior Art
In this type of conventional communication control devices, various control functions required for data communication, for example, a timing control function to transmit and receive communication data, a collision control function to control a collision that happens when two or more data items are output on a network channel simultaneously, and other functions are realized or made up of hardware devices. In those conventional devices, a computer connected to this network is so formed that the computer inputs communication data from external devices and outputs communication data to the external devices. However, in recent years, technique of this communication network field has been increasingly diversified, so that a plurality of protocols are designed, provided, and used widely. It is thereby difficult to apply a communication control device to other communication devices using different other protocols if this communication control device is formed by hardware and the function of one protocol is also realized by the hardware. Conventionally, it must be therefore required to design and make a communication control device for each protocol. In order to avoid this conventional drawback, it is required to form a communication control device in which one function is realized by using a small-sized hardware as small as possible and other functions are formed by using software.
FIG. 5 is a diagram showing a configuration of a conventional communication control device formed based on the above conventional concept. In FIG. 5, the reference number 1 designates an input terminal, connected to communication channels (omitted from FIG. 5), through which communication data items are received, and the reference number 2 indicates an output terminal, connected to the communication channels by using wired OR logic or wired AND logic, through which communication data items are output to outside devices. The reference number 3 denotes a central processing unit (CPU), connected to both the input terminal 1 and the output terminal 2 through a data bus 7, for receiving, processing, and transferring the communication data items. The reference number 4 indicates an input/output port for temporarily storing communication data items transferred through the input terminal I and written by the CPU 3. The reference number 5 designates a timer for counting a clock signal and then for generating and transferring an interrupt signal to the CPU 3 when the timer outputs a time out. The reference number 6 designates a register into which a count value of the timer 5 is set by the CPU 3, and the reference number 7 denotes the data bus group including a plurality of buses through which the CPU 3 is connected to the register 6 and other devices.
Next, a description will be give of the operation of the conventional communication control device shown in FIG. 5.
FIG. 6 is a conceptional diagram of an one-bit wave form used in a LAN communication in which data communication is performed continuously based on the non return to zero (NRZ) method. The conceptional diagram shown in FIG. 6 shows a wave form of a state in which a bit is risen. In FIG. 6, the reference number B designates one bit cycle assigned to one bit, the reference number 9 denotes a transmission point that is a starting edge of one bit, and the reference number 10 indicates a receiving point showing the timing to latch this bit data. The reference number 11 designates a readout setup period having a time length from the transmission point 9 to the receiving point 10, and the reference number 12 denotes an output setup point having a time length from the receiving point 10 to a following transmission point 9 for a following one bit.
In the conventional communication device having the configuration in which the CPU 3 performs various kinds of communication control operations, for example, communication data items are transmitted and received in synchronism with other communication control devices (that is, in synchronism with other communication nodes) according to operation flows as shown in FIGS. 7 and 8.
FIG. 7 is a flow chart of data transmission and receiving control executed by the CPU 3 in order to perform data transmission and receiving operations. In the flow chart shown in FIG. 7, the step ST1 is a timeout waiting step. This step ST1 waits to receive an interrupt signal to be transferred from the timer 5. The step ST2 is an interrupt detection step. In this step ST2, it is detected whether or not this interrupt signal obtained at the step ST1 is an interrupt signal based on a counter value for setting the readout setup period 11. The step ST3 is an output count setting step. This step ST3 is executed only when the interrupt signal obtained by the step ST1 is the interrupt signal based on the counter value to set the readout setup period 11, and the count value to be used for the output setup period 12 is set to the register 6. The step ST4 is a communication data readout step. In this step ST4 to be executed following after the step ST3, the input communication data transferred to the input terminal 1 is read into the communication control device through the input/output port 4. The step ST5 is a collision detection step. In this step ST5, it is checked whether or not the communication data obtained in the step ST4 is equal to the communication data output on the output terminal 2. The step ST6 is a communication stop step. This step ST6 stops the data communication when the comparison result of the step ST5 indicates that both communication data items are different to each other.
The step ST7 is a step to be executed based on the operation result of the step ST2, that is, the step ST7 is executed only when the interrupt signal is obtained based on the count value during the output setup period 12. Further, in the step ST7, the count value for the readout setup period 11 is set into the register 6. The step ST8 is an output terminal writing step, to be executed following the step ST7, in which a communication data item is output to outside devices (not shown) through the output terminal 2 when there is the communication data item. After the completion of the execution of the step ST8, the step ST5 is executed. Specifically, the count value to be set into the register 6 in both the step ST3 and the step ST7 is the value including the interrupt time length from the interrupt generation timing generated by the timer 5 to the timing when the counting by the timer 5 is initiated based on the count value set into the register 6.
FIG. 8 is a flow chart of a data transmission and receiving control executed to compensate the synchronization by the CPU 3 in the conventional communication control device shown in FIG. 5. In FIG. 8, the step ST9 is an edge waiting step in which the edge of the input communication data is detected. The step ST10 is a timing compensation step in which the output count value is set into the register 6. The step ST11 is an edge switching step in which the level of the edge (namely, a rising edge and a falling edge) of the one bit wave form shown in FIG. 6 to be detected is switched.
In the conventional communication control device having such configuration and the function described above, it is possible to set the readout count value and the output count value into the register 6 during the one bit cycle shown in FIG. 6. It is thereby possible to transmit and receive the communication data during the one bit cycle. When both its own communication control device and other communication control device output communication data simultaneously, and when the input communication data and the output communication data are not agreed based on the detection of the wired OR logic or the wired AND logic in its own communication control device, it is possible to halt to output the communication data. On the other hand, when both communication data are agreed to each other, its own communication control device may continue the output of the communication data. Furthermore, because the count value is reset in the conventional communication control device after the edge of the communication data transmitted from the other communication control device is detected, it is possible to keep the operation in synchronization with the operation of other communication control devices (not shown). This causes to provide a stable data communication during a long time period. In addition, it is possible for the conventional communication control device to match various kinds of readout timings and various data communication speeds by changing the ratio between the readout count value and the output count value stored in the register 6.
However, when the communication control device is formed by the minimum size of hardware, for example, the conventional communication control device described above in which the CPU 3 controls various kinds of communication controls, it must be required for the CPU 3 to control all of various kinds of control operations to be required for the data communication. This causes to limit the speed of the data communication by the throughput or the processing ability of the CPU 3. Thus, it is difficult to increase the data communication speed in the conventional communication control device having the above configuration.
Furthermore, when the various kinds of timings of the data communication are controlled based on the interrupt processes described above, it is often happen to shift the synchronization to other communication control devices because there causes a timing lag of several .mu. seconds between the timing when the interrupt request is generated and the timing when the interrupt routine is initiated. In order to avoid the drawback, designers must design the communication control devices while considering the above timing lag and it thereby is difficult to apply the above configuration to communication control devices having protocols for high speed data communication.